Test MP+dmb.sy+ctrl-addr-[fr-rf]-ctrl

AArch64 MP+dmb.sy+ctrl-addr-[fr-rf]-ctrl
"DMB.SYdWW Rfe DpCtrldR DpAddrdR FrLeave RfBack DpCtrldR Fre"
Cycle=Rfe DpCtrldR DpAddrdR FrLeave RfBack DpCtrldR Fre DMB.SYdWW
Relax=
Safe=Rfe Fre DMB.SYdWW DpAddrdR DpCtrldR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe DpCtrldR DpAddrdR FrLeave RfBack DpCtrldR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=z; 1:X6=a; 1:X9=x;
2:X1=a;
}
 P0          | P1                  | P2          ;
 MOV W0,#1   | LDR W0,[X1]         | MOV W0,#1   ;
 STR W0,[X1] | CBNZ W0,LC00        | STR W0,[X1] ;
 DMB SY      | LC00:               |             ;
 MOV W2,#1   | LDR W2,[X3]         |             ;
 STR W2,[X3] | EOR W4,W2,W2        |             ;
             | LDR W5,[X6,W4,SXTW] |             ;
             | LDR W7,[X6]         |             ;
             | CBNZ W7,LC01        |             ;
             | LC01:               |             ;
             | LDR W8,[X9]         |             ;
Observed
    y=1; x=1; a=1; 1:X8=1; 1:X7=0; 1:X5=1; 1:X0=1;
and y=1; x=1; a=1; 1:X8=0; 1:X7=0; 1:X5=1; 1:X0=1;
and y=1; x=1; a=1; 1:X8=1; 1:X7=0; 1:X5=1; 1:X0=0;
and y=1; x=1; a=1; 1:X8=0; 1:X7=0; 1:X5=1; 1:X0=0;